The present invention relates generally to integrated circuits, and, more particularly, to a system for reducing power consumption of integrated circuits.
Integrated circuits are designed using digital logic elements including logic gates and combinational logic circuits. The digital logic elements include complementary metal-oxide semiconductor (CMOS) circuits. CMOS circuits consume power, which leads to high power dissipation and increases junction temperatures of the integrated circuits. Power dissipation is also a concern, especially for low power circuits that run on batteries because excessive power consumption reduces battery charge more quickly.
FIG. 1 shows a chart illustrating power dissipation in an integrated circuit (IC) for a sample design in a particular process technology node. This is shown for illustrating a trend of power break-up within a design As can be seen, dynamic power accounts for nearly 60% of the power consumed and leakage accounts for the remaining 40% in deep sub micron technology nodes. Within the dynamic power consumption, there is short circuit power and switching power. Switching power is dissipated by CMOS circuits by charging and discharging various load capacitances (gate/wire/source/drain capacitances) of the transistors. Switching power can be broken down into gate capacitance power and interconnect power, with interconnect power being further broken down into data interconnect power and clock interconnect power, where FIG. 1 shows that data interconnect power accounts for nearly 21.6% of power consumption and clock interconnects only 2.4%. Therefore, it would make sense to try to reduce this data power consumption.